module led(
	input [4:0] in_req,
	input [4:0] in_reqR,//
	input [4:0] out_requp,
	input [4:0] out_reqdown,

	output reg [3:0] ledup,
	output reg [3:0] leddown,
	output reg [4:0] ledinL,
	output reg [4:0] ledinR//
);
initial
	begin
	ledup <= 4'b0000;
	leddown <= 4'b0000;
	ledinL <= 5'b00000;
	ledinR <= 5'b00000;
	end

always@(*)
begin
ledinL <= in_req;
ledinR <= in_reqR;
ledup[3:0] <= out_requp[3:0];
leddown[3:0] <= out_reqdown[4:1];
end
endmodule
